Sept.
17 2004 - for immediate release: Sept.
17 2004 - for immediate release:
J-LINK REDUCES JTAG DEBUG PINCOUNT FROM 5 to 1!
Pittsford, New York. Traditional JTAG boundary-scan testing normally takes up 5 valuable pins on an i.c., requires 5 resistors, and increases chip power. The revolutionary new J-LINK system requires only one pin and two resistors, and reduces chip consumption, providing full speed JTAG debug access to a device through a single pin while maintaining compatibility with existing debug tools.
Pincount and real-estate reduction are prime concerns for space-constrained,
frugal chip designers. In addition, with J-LINK, standard JTAG debug test-gear
needn’t be changed at all to use just one pin instead of five - an external
J-LINK adapter retrieves the conventional five lines.
Conceived in Europe by Debug Innovations Ltd, J-LINK is an innovative new
concept, set to revolutionize the world of JTAG debug. Its impact will be seen
in many manufacturer’s chips in the near future. Since the emergence of the IEEE
1149.1 JTAG standard, all chips with boundary scan have 5 device pins allocated
to enable access to the boundary scan circuitry. This has simplified both board
and device testing using scan test methods. Software debug architects have
adopted this same system to gain access to devices for software development and
debug. It’s been this way for over a decade. The push for greater functionality
and smaller footprint devices while still maintaining good access for debug and
test has put pressure on chip manufacturers to increase device pin count. This
in turn pushes up the size and cost of a device and/or decreases the pitch of
its pins. The result is a ‘debug dilemma’ - high performance processors require
a comprehensive test and debug system, but the 5 precious debug pins may be
needed for other functions.
J-LINK
solves this dilemma by reducing the number of JTAG pins required to just one.
This is of great importance to manufacturers of low pin count microcontrollers.
The J-LINK system consists of a small piece of on-chip logic known as the
‘interface circuit’, and an external ‘converter box’ which interfaces J-LINK to
standard JTAG testers or in-circuit emulators (ICEs). It immediately enables
designers to test and debug devices with standard JTAG interfaces using only
one device pin, an essential feature for low pin count devices.
Since
JTAG was not originally designed for i.c. debugging, a chip with a JTAG debug
system has no knowledge of whether it is being used for debug. This means that
any debug blocks have to be permanently enabled 'just in case' a debugger is
connected. Of course most of the time, in the product application, those debug
blocks will never be used and are simply consuming power unnecessarily. The
J-LINK interface circuit understands when it is being used for debug and
provides an output that can be used to turn off any 'debug only' blocks on your
device. For every pin, you need a pad, so less pins means less pads. With
modern process geometries, pads can take up a large proportion of the Silicon
area. In contrast the J-LINK interface circuit is tiny, taking up less area
than one pad. In a 100 pin ASIC, if the pads take up 25% of the Silicon area,
then removing 5 pads will reduce the area by over 1%. So, in addition to
substantial package savings, the Silicon costs will reduce by 1% and yields will
improve because there are less bond wires.
J-LINK is
now available for licensing to semiconductor companies who wish to reduce the
number of pins required for JTAG from the traditional five down to a single pin
without loss of debug performance. The J-LINK design is suitable for use with
any JTAG compatible device and a number of converter boxes are available to suit
different ICE designs. J-LINK will be demonstrated during the ARM Developer’s
Conference during 19-21st Oct at the Santa Clara Convention Center in
Santa Clara, California.
More at www.debuginnovations.com
Refpr091704debug