W7200Saelig Logo

 

 

 

NEW PRODUCT ANNOUNCEMENT
FOR IMMEDIATE RELEASE
: March 8, 2012
Contact:
   Alan Lowne, CEO, Saelig Co. Inc.
                    Tel: (585) 385-1750
                    Email: info@saelig.com



Saelig Introduces New ARM + Hardwired TCP/IP Chip


Pittsford, NY:  The W7200 is a new single chip microcontroller which integrates an ARM 32bit Cortex M3 with a hardwired TCP/IP core for high performance, easy development, and instant-on, reliable Ethernet capabilities.  The W7200 incorporates 10BaseT/100BaseTX Ethernet PHY (physical layer), supporting half-duplex/full-duplex, auto-negotiation, and auto-MDI/MDIX. W7200 has been created by integrating an ARM STM32F103CB MCU and WIZnet’s popular hardwired TCP/IP chip W5200 on the same IC layout. The STM32F103CB MCU portion provides the GPIO, I2C, SPI, USB and USART capabilities, while the SPI-connected W5200 layout provides the stable TCP/IP Stack, MAC and Ethernet PHY.

Using a standard ARM core means that the W7200 is compatible with readily-available existing ARM tools and software. The ARM Cortex M3 processor is the latest generation of ARM processors for embedded systems, providing a low-cost MCU platform with reduced pin count and low-power consumption.  This 32-bit ARM RISC processor delivers outstanding computational performance with an advanced system response to interrupts.  It features exceptional code-efficiency, delivering high performance in a compact memory size that is more often associated with smaller 8- and 16-bit devices.

Offloading the TCP/IP stack to an external chip block is an excellent strategy for speeding up product development time, avoiding crashes and addressing inherent unreliability. Offloading reduces CPU burden and improves overall system performance. Software TCP/IP processing load is not usually much of a problem given unlimited development time, lots of memory space, and a fast environment. But with embedded systems having limited resources, and with obstacles such as cost, power consumption, and board real estate to be overcome, software TCP/IP stacks can cause issues, especially when considering the future upgrading of in-service system firmware. And with a software TCP/IP stack, interrupts can cause variable processing delays, which is never a problem with W7200’s independent Ethernet communication. 

The W7200’s TCP/IP Core is composed of a fully-hardwired, market-proven TCP/IP stack and an integrated Ethernet MAC & PHY.  Wiznet’s hardwired TCP/IP stack has been designed into thousands of products over many years, supporting TCP, UDP, IPv4, ICMP, ARP, IGMP, and PPPoE protocols. The TCP/IP Core can run up to 8 independent sockets simultaneously. With the W7200, Ethernet capabilities can be implemented by using a simple socket program instead of dealing with a complex Ethernet Controller. In order to reduce system power consumption, the TCP/IP Core provides WOL (Wake on LAN) and Sleep, Stop and Standby power-down modes.  The W7200 also supports 6 LED outputs for Link, TX, RX status, Collision, Speed, and Duplex indicators.

The W7200 is supplied in a 10mm x 10mm LGA60 package and incorporates: 7 timers, including three 16-bit timers (each with up to 4 IC/OC/PWM or pulse counter and quadrature/incremental encoder input), two watchdog timers (Independent and Window), and a SysTick timer 24-bit down counter; 20KBytes Data Memory (RAM); 128KBytes Code Memory; a CRC calculation function (96-bit unique ID); GPIO, SPI, USART and USB Interfaces; embedded 32Kbyte data buffer for networking.

The W7200 and demo boards will be available Q2 2012 from WIZnet's USA distributor Saelig Company.

 

Hi-res Image

Order on-line HERE

 

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